We present our recent work on monolithically integrated devices comprising a variety of functional elements such as high speed optical transmitters and receivers, electro-absorption modulators integrated with tunable dispersion compensators and fast-tunable wavelength converters.

This letter presents a race-free mixed serial-parallel comparison (RFMSPC) scheme which uses both serial and parallel CAMs in a match line. A self-reset search line scheme for the serial CAM is proposed to avoid the timing race problem and additional timing penalties. Various 32 entry CAMs are designed using 90 nm 1.2 V CMOS process to verify the proposed RFMSPC scheme. It shows that the RFMSPC saves power consumption by 40%, 53% and 63% at the cost of a 4%, 6% and 16% increase in search time according to 1, 2, and 4 serial CAM bits in a match line.

The possibility of using three kinds of new type composite materials as material for high speed sliding contacts was investigated. The results of this investigation were compared with the results of the low speed tests that were reported earlier. As a result of the above, it was discovered that for high speed rotation in the range from 0.014 m/s to 2 m/s, the order of merit did not significantly change. Based on this, it was concluded that if solid lubricant is effectively supplied to the sliding surface, the influence by frictional heat generated by high speed is slight. Of the three kinds of composite material, it was clarified that composite material (CMML-1) had the lowest contact resistance and Composite Material (CMML-3) had the lowest maximum frictional coefficient of friction. 'CM' and 'ML' are initialisms for 'Composite Material' and 'Material of Lubrication' respectively. The number that is attached to the material name is a numeric value that was set by this laboratory.

A new level shifter is proposed in this paper that mitigates the contention problem between its pull-up and pull-down switches without suffering the delay penalty. Comparing this new one with two conventional shifters (CLS-1 and CLS-2) indicates that CLS-1 and CLS-2 have the delay times which are 308% and 26% slower than the proposed shifter when VDDL/VDDH=0.3 and the fan-out=2, respectively. In addition, the comparison of power-delay products shows CLS-2 consumes 28.5% more energy than the proposed shifter. For the layout area, the proposed shifter needs only 15% more than CLS-2. By comparing the propagation delay times, the power-delay products, and the area overhead, the proposed shifter is considered very suitable to future Very Deep Sub-Micron (VDSM) technologies with low-voltage applications.

A novel configuration method called Row Multicast Configuration (RoMultiC) is proposed for high speed configuration of coarse grain reconfigurable systems. The same configuration data can be transferred in multicast fashion to configure many Processing Elements (PEs) by using a multicast bit-map provided in row and column directions of PE array. Evaluation results using practical applications show that a model reconfigurable system that incorporates this scheme can reduce configuration clock cycles by up to 73.1% compared with traditional configuration delivery scheme. Amount of required memory to store the configuration data at external memory is also reduced by omitting the duplicated configuration data.

The uni-traveling-carrier photodiode (UTC-PD) is an innovative PD that has a unique operation mode in which only electrons act as the active carriers, resulting in ultrafast response and high electrical output power at the same time. This paper describes the features of the UTC-PD and its excellent performance. In addition, UTC-PD-based optoelectronic devices integrated with various elements, such as passive and active devices, are presented. These devices are promising for various applications, such as millimeter- and submillimeter-wave generation up to the terahertz range and ultrafast optical signal processing at data rates of up to 320 Gbit/s.

A 1-Gb AG-AND flash memory has been fabricated using 0.13-µm CMOS technology, resulting in a cell area of 0.104 µm2 and a chip area of 95.2 mm2. By applying constant-charge-injection programming and source-line-select programming, a fast page programming time of 600 µs is achieved. The four-bank operation attains a fast programming throughput of 10 MB/s in multilevel flash memories. The compact SRAM write buffers reduce the chip area penalty. A rewrite throughput of 8.3 MB/s is achieved by means of the RAM-write operation during the erase mode.

With advent of the ubiquitous network era and due to recent progress of III-V nanotechnology, the present III-V heterostructure microelectronics will turn into what one might call III-V heterostructure nanoelectronics, and may open up a new future in much wider application areas than today, combining information technology, nanotechnology and biotechnology. Instead of the traditional top-down approach, new III-V heterostructure nanoelectronics will be formed on nanostructure networks formed by combination of top-down and bottom-up approaches. In addition to communication devices, emerging devices include high speed digital LSIs, various sensors, various smart-chips, quantum LSIs and quantum computation devices covering varieties of application areas. Ultra-low power quantum LSIs may become brains of smart chips and other nano-space systems. Achievements of new functions and higher performances and their on chip integration are key issues. Key processing issue remains to be understanding and control of nanostructure surfaces and interfaces in atomic scale.

Various mixed-signal very-high-speed integrated circuits have been developed using InP DHBTs. These circuits have been designed for fiber-optic 43 Gbit/s transmissions applications. They include: on the transmitting side, a clocked driver and an EAM driver, as well as a PSBT/DQPSK precoder; on the receiving side, a sensitive decision circuit, a limiting amplifier and an eye monitor. System experiments made possible by these circuits include a 6 Tbit/s transmission on >6000 km distance.

It is well known that TCP does not fully utilize the available bandwidth in fast long-distance networks. To solve this scalability problem, several high speed transport protocols have been proposed. They include HighSpeed TCP (HS-TCP), Scalable TCP (S-TCP), Binary increase control TCP (BIC-TCP), and H-TCP. These protocols increase (decrease) their window size more aggressively (slowly) compared to standard TCP (STD-TCP). This paper aims at evaluating and comparing these high speed transport protocols through computer simulations. We select six metrics that are important for high speed protocols; scalability, buffer requirement, TCP friendliness, TCP compatibility, RTT fairness, and responsiveness. Simulation scenarios are carefully designed to investigate the performance of these protocols in terms of the metrics. Results clarify that each high speed protocol successfully solves the problem of STD-TCP. In terms of the buffer requirement, S-TCP and BIC-TCP have better performance. For TCP friendliness and compatibility, HS-TCP and H-TCP offer better performance. For RTT fairness, BIC-TCP and H-TCP are superior. For responsiveness, HS-TCP and H-TCP are preferred. However, H-TCP achieves a high degree of fairness at the expense of the link utilization. Thus, we understand that all the proposed high speed transport protocols have their own shortcomings. Thus, much more research is needed on high speed transport protocols.

This paper proposes a logic synthesis technique for asymmetric slope differential dynamic logic (ASDDL) circuits. The technique utilizes a commercially available logic synthesis tool that has been well established for static CMOS logic design, where an intermediate library is devised for logic synthesis likely as static CMOS, and then a resulting synthesized circuit is translated automatically into ASDDL implementation at the gate-level logic schematic level as well as at the physical-layout level. A design example of an ASDDL 16-bit multiplier synthesized in a 0.18-µm CMOS technology shows an operation delay time of 1.82 nsec, which is a 32% improvement over a static CMOS design with a static logic standard-cell library that is finely tuned for energy-delay products. Design with the 16-bit multiplier led to a design time for an ASDDL based dynamic digital circuit 300 times shorter than that using a fully handcrafted design, and comparable with a static CMOS design.

We aim to establish a highly efficient transmitting power control (TPC) scheme suitable for the reverse link of high-speed CDMA packet communication systems. Reservation-based access is assumed to be used for packet transmission in the reverse link. First, we describe a hybrid TPC that we created to cope with average interference changes. The target receiving power in the hybrid TPC is set according to the interference averaged over a comparatively long period of time. We show, using experiments on our high-speed packet communication experimental system, that hybrid TPC can effectively reduce transmission power consumption and PER compared with basic receiving power based TPC. Furthermore, we need to change the transmitting power according to the instantaneous interference to cope with instantaneous interference changes slot by slot. However, in a high-speed packet communication system, the interference level can change dramatically in a very short period of time. The TPC of cdma2000 or W-CDMA cannot efficiently cope with rapidly and greatly changing interference levels. Therefore, we created another two novel TPCs. Interference is divided in these TPCs into intra-cell and inter-cell interference. The supposed inter-cell interference level is changed according to the change in the probability distribution of the inter-cell interference, and the necessary transmitting power for a packet is calculated based on intra-cell allocation information and the supposed inter-cell interference level. Computer simulations show that, with the proposed TPCs, throughput can be increased by more than 200% compared with the type of TPC used in cdma2000 or W-CDMA, and the transmitting power consumption in a mobile host (MH) can also be vastly reduced.

Asymmetric slope differential CMOS (ASD-CMOS) and asymmetric slope differential dynamic logic (ASDDL) surpass the highest speed that conventional CMOS logic circuits can achieve, resulting from deeply shortened rise time along with relatively prolonged fall time. ASD-CMOS is a static logic and ASDDL is a dynamic logic without per-gate synchronous clock signal, each of which needs two-phase operation as well as differential signaling, however, interleaved precharging hides the prolonged fall time and BDD-based compound logic design mitigates area increase. ASD-CMOS 16-bit multiplier in a 0.18-µm CMOS technology demonstrates 1.78 nsec per an operation, which reaches 34% reduction of the best delay time achieved by a multiplier using a CMOS standard cell library that is conventional yet tuned to the optimum in energy-delay products. ASDDL can be superior to DCVS-DOMINO circuits not only in delay time but also in area and even in power. ASDDL 16-bit multiplier achieves delay and power reduction of 4% and 20%, respectively, compared with DCVS-DOMINO realization. A prototype ASD-CMOS 16-bit multiplier with built-in test circuitry fabricated in a 0.13-µm CMOS technology operates with the delay time of 1.57 nsec at 1.2 V.

We have proposed diffusion-type flow control as a solution for the extremely time-sensitive flow control required for high-speed networks. In our method of flow control, we design in advance simple and appropriate rules for action at the nodes, and these automatically result in stable and efficient network-wide performance through local interactions between nodes. Specifically, we design the rules for the flow control action of each node that simulates the local interaction of a diffusion phenomenon, in order that the packet density is diffused throughout the network as soon as possible. However, in order to make a comparison with other flow control methods under the same conditions, the evaluations in our previous studies used a closed network model, in which the number of packets was unchanged. This paper investigates the performance of our flow control method for an end-to-end flow, in order to show that it is still effective in more realistic networks. We identify the key issues associated with our flow control method when applied to an open network model, and demonstrate a two-step solution. First, we consider the rule for flow control action at the boundary node, which is the ingress node in the network, and propose a rule to achieve smooth diffusion of the packet density. Secondly, we introduce a shaping mechanism, which keeps the number of packets in the network at an appropriate level.

This paper describes two circuit techniques useful for the design of high density and high speed low cost double data rate memories. One is a highly flexible row and column redundancy circuit which allows the division of flexible row redundancy unit into multiple column redundancy unit for higher flexibility, with a new test mode circuit which enables the use of the finer pitch laser fuse. Another is a compact read data path which allows the smooth data flow without wait time in the high frequency operation with less area penalty. These circuit techniques achieved the compact chip size with the cell efficiency of 60.6% and the high bandwidth of 400 MHz operation with CL=2.5.

This paper proposes a cell layout synthesis method via Boolean Satisfiability (SAT). Cell layout synthesis problems are first transformed into SAT problems by our formulations. Our method realizes a high-speed layout synthesis for CMOS logic cells and guarantees to generate the minimum-width cells with routability under our layout styles. It considers complementary P-/N-MOSFETs individually during transistor placement, and can generate smaller width layout compared with pairing the complementary P-/N-MOSFETs case. To demonstrate the effectiveness of our SAT-based cell synthesis, we present experimental results which compare it with the 0-1 ILP-based transistor placement method and a commercial cell generation tool. The experimental results show that our SAT-based method can generate minimum-width placements in much shorter run time than the 0-1 ILP-based transistor placement method, and can generate the cell layouts of 32 static dual CMOS logic circuits in 54% run time compared with the commercial tool. Area increase of our method without compaction is only 3% compared with the commercial tool with compaction.

A principal attraction of ATM networks, in both wired and wireless realizations, is that the key quality of service (QoS) parameters of every call, including end-to-end delay, jitter, and loss are guaranteed by the network when appropriate cell-level traffic controls are imposed at the user network interface (UNI) on a per call basis, utilizing the peak cell rate (PCR) and the sustainable cell rate (SCR) values for the multimedia--voice, video, and data, traffic sources. There are three practical difficulties with these guarantees. First, while PCR and SCR values are, in general, difficult to obtain for traffic sources, the typical user-provided parameter is a combination of the PCR, SCR, and the maximum burstiness over the entire duration of the traffic. Second, the difficulty in accurately defining PCR arises from the requirement that the smallest time interval must be specified over which the PCR is computed which, in the limit, will approach zero or the network's resolution of time. Third, the literature does not contain any reference to a scientific principle underlying these guarantees. Under these circumstances, the issue of providing QoS guarantees in the real world, through traffic controls applied on a per call basis, is rendered uncertain. This paper adopts a radically different, high level approach to the issue of QoS guarantees. It aims at uncovering through systematic experimentation a relationship, if any exists, between the key high level user traffic characteristics and the resulting QoS measures in a realistic operational environment. It may be observed that while each user is solely interested in the QoS of his/her own traffic, the network provider cares for two factors: (1) Maximize the link utilization in the network since links constitute a significant investment, and (2) ensure the QoS guarantees for every user traffic, thereby maintaining customer satisfaction. Based on the observations, this paper proposes a two-phase strategy. Under the first phase, the average "link utilization" computed over all the links in a network is maintained within a range, specified by the underlying network provider, through high level call admission control, i.e. by limiting the volume of the incident traffic on the network, at any time. The second phase is based on the hypothesis that the number of traffic sources, their nature--audio, video, or data, and the bandwidth distribution of the source traffic, admitted subject to a specific chosen value of "link utilization" in the network, will exert a unique influence on the cumulative delay distribution at the buffers of the representative nodes and, hence, on the QoS guarantees of each call. The underlying thinking is as follows. The cumulative buffer delay distribution, at any given node and at any time instant, will clearly reflect the cumulative effect of the traffic distributions of the multiple connections that are currently active on the input links. Any bounds imposed on the cumulative buffer delay distribution at the nodes of the network will also dominate the QoS bounds of each of the constituent user traffic. Thus, for each individual traffic source, the buffer delay distributions at the nodes of the network, obtained for different traffic distributions, may serve as its QoS measure. If the hypothesis is proven true, in essence, the number of traffic sources and their bandwidth distribution will serve asa practically realizable high level traffic control in providing realistic QoS guarantees for every call. To verify the correctness of the hypothesis, an experiment is designed that consists of a representative ATM network, traffic sources that are characterized through representative and realistic user-provided parameters, and a given set of input traffic volumes appropriate for a network provider approved link utilization measure. The key source traffic parameters include the number of sources that are incident on the network and the constituent links at any given time, the bandwidth requirement of the sources, and their nature. For each call, the constituent cells are generated stochastically, utilizing the typical user-provided parameter as an estimate of the bandwidth requirement. Extensive simulations reveal that, for a given link utilization level held uniform throughout the network, while the QoS metrics--end-to-end cell delay, jitter, and loss, are superior in the presence of many calls each with low bandwidth requirement, they are significantly worse when the network carries fewer calls of very high bandwidths. The findings demonstrate the feasibility of guaranteeing QoS for each and every call through high level traffic controls. As for practicality, call durations are relatively long, ranging from ms to even minutes, thereby enabling network management to exercise realistic controls over them, even in a geographically widely dispersed ATM network. In contrast, current traffic controls that act on ATM cells at the UNI face formidable challenge from high bandwidth traffic where cell lifetimes may be extremely short, in the range of µs. The findings also underscore two additional important contributions of this paper. First, the network provider may collect data on the high level user traffic characteristics, compute the corresponding average link utilization in the network, and measure the cumulative buffer delay distributions at the nodes, in an operational network. The provider may then determine, based on all relevant criteria, a range of input and system parameters over which the network may be permitted to operate, the intersection of all of which may yield a realistic network operating point (NOP). During subsequent operation of the network, the network provider may guide and maintain the network at a desired NOP by exercising control over the input and system parameters including link utilization, call admittance based on the requested bandwidth, etc. Second, the finding constitutes a vulnerability of ATM networks which a perpetrator may exploit to launch a performance attack.

A low-power microcontroller has been developed with 0.10 µm bulk compatible body-tied SOI technology. For this work, only two new masks are required. For the other layers, existing masks of a prior work developed with 0.18 µm bulk CMOS technology can be applied without any changes. With the SOI technology, the high-speed operation of over 600 MHz has been achieved at a supply voltage of 1.2 V, which is 1.5 times faster than prior work. Also, a five times improvement in the power-delay product has been achieved at a supply voltage 0.8 V. Moreover, the compatibility of the SOI technology with bulk CMOS has been verified, because all circuit blocks of the chip, including logic, memory, analog circuit, and PLL, are completely functional, even though only two new masks are used.

Channel estimation is one of the key technologies in mobile communications. Channel estimation is critical in providing high data rate services and to overcome fast fading in very high-speed mobile communications. This paper presents a novel channel estimation based on hybrid spreading of I and Q signals (CEHS). Simulation results show that it can effectively mitigate the influence of fast fading and enable to provide high data rates for very high speed mobile systems.

A high-speed 3-D camera has a future possibility of wide variety of application fields such as quick inspection of industrial components, observation of motion/destruction of a target object, and fast collision prevention. In this paper, a row-parallel position detector for a high-speed 3-D camera based on a light-section method is presented. In our row-parallel search method, the positions of activated pixels are quickly detected by a row-parallel search circuit in pixel and a row-parallel address acquisition of O(log N) cycles in N-pixel horizontal resolution. The architecture keeps high-speed position detection in high pixel resolution. We have designed and fabricated the prototype position sensor with a 12816 pixel array in 0.35 µm CMOS process. The measurement results show it achieves quick activated-position acquisition of 450 ns for "beyond-real-time" 3-D imaging and visual feedback. The high-speed position detection of the scanning sheet beam is demonstrated.